What is SystemVerilog? An extension of Verilog by Iteso

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What is system Verilog? Santiago Miguel Segovia CázaresWhat is a HDL? It is a high level language used to describe hardware.

SystemVerilog Overview

SystemVerilog is a standard set of extensions to the IEEE 1364-2005 Verilog Standard. SystemVerilog integrates hardware description language and object-oriented programing. SystemVerilog is defined as a Hardware description and verification language (HDVL). > SystemVerilog also contains many extensions for the verification of large designs, integrating features from the SUPERLOG, VERA C, C++, and VHDL languages, along with OVA and PSL assertions With SystemVerilog you can model at a much higher level of data abstraction than Verilog, and yet be fully synthesizable.

SystemVerilog as a Superset of Verilog

System Verilog is super-set of verilog. All syntax elements in verilog are valid in SystemVerilog. System Verilog Verilog

Concurrent and Sequential Behavior

> The structural and data flow descriptions have a concurrent behavior. All statements are "executed" concurrently, and the order of the statements does not matter. , On the other hand, behavioral descriptions are executed sequentially in always blocks, tasks and functions in Verilog. The behavioral descriptions may be similar to high-level programming languages. 5

SystemVerilog Sentence Grouping

System Verilog sentences as other HDLs can be grouped as: · Synthesizable · Sentences that can produce hardware. · Non-synthesizable · Sentence that can't produce hardware

SystemVerilog Simulation and Synthesis

> All sentences in SystemVerilog can be simulated, but not completely synthesizable. > There are a number of SystemVerilog constructs that have no valid representation in a digital circuit. Other constructs do, in theory, have a representation in a digital circuits, but cannot be reproduced with guaranteed accuracy. Delay time modeling in Verilog is an example of that. 7

Synthesis of SystemVerilog Descriptions

> Therefore, the result of synthesis of a System Verilog description depends on the style of SystemVerilog that is used. , You should understand some of the concepts of synthesis specific to SystemVerilog coding style at the RTL level, in order to achieve the desired circuit implementation. 8

Module in SystemVerilog

The basic design unit in SystemVerilog is the module. > It represents an abstraction from the real world. > It is defined by its interface. The interface contains parameters and ports. Parameters are constants that helps to configure the module. Ports represents the physical ports in the design. Ports can be: · input · output ◦ inout 9

Numeric Representation in SystemVerilog

Sytem Verilog supports four values and eight strengths to model the functionality of real hardware: · X: Unknown logic value · Z: High impedance, floating state · 0: Logic zero, false condition · 1 : Logic one, true condition Numeric representation is expressed as Number of bits 'radix value

Numeric Representation Examples

Numeric representation Binary equivalent Explanation 4'd5 0101 Decimal value 5 as a 4 bits signal. 8'b101 00000101 Binary 101 converted to an 8 bits signal. 12'h5B_3 010110110011 0x5B3 with 12 bits length. Underscore is used just as a splitter. -8'b101 11111011 Negative 101 at 8 bits length. 10'0752 0111101010 Octal 752 with 10 bits length. 8'hF 00001111 0xF extended to 8 bits length (not signed, i.e. filled with 0s)

Representación Numérica

Numeric representation Binary equivalent Explanation 12'hXA xxxxxxxx1010 0xA as a 12 bits signal. Higher bits filled with x values. 12'shA6 Signed 111110100110 0xA6 extended at 12 bits (signed, i.e. repeated MSB). -4'shA Signed 0110 Negative 0xA as a signed value of 4 bits. 596 1001010100 Constant.

Data Types in SystemVerilog

Numeric data types. String types. > User-defined types. Emun types. Struct type. Union type. > Arrays.

Numeric Data Types Table

Type Description Note integer 4 states, 32 bits, signed integer Verilog data types reg 4 states, user-defined size real Float of 64 bits time 4 states, 64 bits, signed integer realtime 4 states, 64 bits, signed integer shortint 2 states (1,0), 16 bits, signed integer Int 2 states 32 bits, signed integer Long int 2 states, 64 bits, signed integer bit 2 states, 1 bit byte 2 states, 8 bits, signed integer logic 4 states, user-defined size shortreal Float of 32 bits void void Systemverilog data types

Reg and Logic Types

› In Verilog we use reg type to describe either sequential or combinational logic, which implies uncertainty on some descriptions. > System Verilog fix this problem by creating logic type and new always processes. Important! Rest of types could be used to describe hardware.

Net in SystemVerilog

A Net represents a connection between hardware elements or in-ports of a device > They can be scalar or vectorial. > They are constantly assigned by outputs of devices connected to them. b C AND a Net a is connected to output of AND gate, net a will constantly receive assignation of the logic operation B & c. > Wire is the element we use to connect nets to other modules.

Constants in SystemVerilog

> SystemVerilog supports four types of constants: · parameter · Localparam · specparam · const Parameter is used when it should be accessible out of the module. Localparam becomes read-only (write protection). Specparam is used to define temporal constants. const is used for constant values.

Constant Declaration Examples

› Parameter · parameter port_id =5; · parameter cache_line_width = 256; Localparameter · localparam initial_state = 2; · localparam constante = 4'b1100; > Constant · const logic [23:0] C1 = 7; / / 24-bit constant · const int C2 = 15; / / 32-bit constant · const real C3 = 3.14; / / real constant · const C4 = 5; / / ERROR, no type

Operators in Verilog and SystemVerilog

Arithmetic Operators

Type Symbol Name Operators' count Arithmetic + Sum Multiple Subtraction Multiple * Multiply Multiple / Division Multiple ** Power Multiple

Logical Operators

Logical ! Not One && And Two | Or Two

Relational Operators

Type Symbol Name Operators' count Relational > Greater than Two < Less than Two >= Greater than or equal to Two <= Less than or equal to Two

Equality Operators

Equality == Equal to Two != Not equal to Two Equal to 'case' Two Not equal to 'case' Two

Bitwise Operators

Type Symbol Name Operators' count Bitwise ~ Not One & And Two | Or Two ^ Xor Two Xnor Two

Reduction Operators

Reduction & And One ~& Nand One | Or One ~ Nor One ^ Xor One Xnor One

Shifting Operators

Type Symbol Name Operators' count Shifting >> Right shift Two Left shift Two >>> Arithmetic right shift Two <<< Arithmetic left shift Two

Concatenation and Replication Operators

Concatenation Concatenation Any number Replication Replication Any number

Conditional Operator

Conditional ?: Conditional Any number

Operators for SystemVerilog

Type Symbol assignation +=, == , *= , /=, %=, &=, |=, ^=, <<= , >>=, <<<= , >>>= Self- increment/decrement ++, -- Logical evaluation -> <- > Packing {<<{}},

Operators Priority

Highest + - ! ~ * * * / % + - << >> <<< >>> == ! = === != & ~ & 11-21 & & = ? : Lowest

Constants in Verilog

Constants in Verilog are declared by parameters. Parameters are not nets nor regs. They cannot be used as variables They are assigned during compilation process Parameters can use default value or been overwritten.

References

What is system Verilog? By Jose Luis Pizano.